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authorElyes HAOUAS <ehaouas@noos.fr>2019-03-29 17:12:15 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-04-23 10:01:36 +0000
commitcd4fe0f718cfc49e5d58f1770e23cd065a26241e (patch)
treea1b335fc76f89e79480456e3c6cd1672f4eefb2c /src/soc/intel/cannonlake
parent351e3e520ba71b4aafaf930af37f78b71c1d7251 (diff)
src: include <assert.h> when appropriate
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/romstage/romstage.c1
-rw-r--r--src/soc/intel/cannonlake/uart.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 893f37d421..c168da9a38 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <assert.h>
#include <chip.h>
#include <cpu/x86/mtrr.h>
#include <cbmem.h>
diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c
index 1b72b24d5f..2bd906adf8 100644
--- a/src/soc/intel/cannonlake/uart.c
+++ b/src/soc/intel/cannonlake/uart.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <assert.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <intelblocks/gpio.h>