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authorPraveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>2018-10-23 02:43:05 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-10-25 09:26:50 +0000
commitb66757fc58b9bd025148d9db690009dec487fd0d (patch)
tree419a761bf317a4c56068309e997248d9a75fe8cf /src/soc/intel/cannonlake
parentac6a5080ecb0288c980493cec8e43be2b7490aa3 (diff)
soc/intel: Consolidate FSP CAR setup and teardown code
This patch adds following changes, - APL, CFL, DENVERTON soc's using same implementation to setup and teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is cosolidated into one file and moved to common code CPU car folder. - exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file and moved to common CPU car. - The new file apollolake/fspcar.c is addded to pass tempraminit parameters. - Coffee lake Soc uses FSPT to support Intel Security features like BootGuard verify boot and Measured boot. Add FSP CAR support for CFL by programming tempraminit parameters and add FSP_T_XIP default if FSP_CAR is selected. BUG= None TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup. Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR without errors. Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9 Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/29209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/Kconfig1
-rw-r--r--src/soc/intel/cannonlake/bootblock/bootblock.c20
2 files changed, 20 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index abe029a194..161db33217 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -75,6 +75,7 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC
select UDK_2017_BINDING
select DISPLAY_FSP_VERSION_INFO
+ select FSP_T_XIP if FSP_CAR
config UART_DEBUG
bool "Enable UART debug port."
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c
index 0aac186b42..4eeef59e4d 100644
--- a/src/soc/intel/cannonlake/bootblock/bootblock.c
+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corporation..
+ * Copyright (C) 2017-2018 Intel Corporation..
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -19,6 +19,24 @@
#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <soc/pch.h>
+#include <FsptUpd.h>
+
+const FSPT_UPD temp_ram_init_params = {
+ .FspUpdHeader = {
+ .Signature = 0x545F4450554C4643ULL, /* 'CFLUPD_T' */
+ .Revision = 1,
+ .Reserved = {0},
+ },
+ .FsptCoreUpd = {
+ .MicrocodeRegionBase =
+ (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC,
+ .MicrocodeRegionSize =
+ (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN,
+ .CodeRegionBase =
+ (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
+ .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,
+ },
+};
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{