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authorFelix Singer <felixsinger@posteo.net>2020-12-07 01:28:59 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2020-12-08 21:16:30 +0000
commit1e3b2ce061626e6c5a7d7f89d40a854bac16f3d4 (patch)
treeb4c9e92a814f0cb0d75233d5d1526fbb707a6e8e /src/soc/intel/cannonlake
parent77562cf95e8b5911919fc346949bc17eb32d8b87 (diff)
soc/intel/cannonlake: Align SATA mode names with soc/skl
Align the SATA mode names with soc/skl providing a consistent API. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/chip.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index a084f67b46..70aab92853 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -129,8 +129,8 @@ struct soc_intel_cannonlake_config {
/* SATA related */
enum {
- Sata_AHCI,
- Sata_RAID,
+ SATA_AHCI,
+ SATA_RAID,
} SataMode;
/* SATA devslp pad reset configuration */