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| author | Joe Moore <awokd@danwin1210.me> | 2019-10-21 03:32:38 -0600 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-13 11:22:40 +0000 |
| commit | 159cd3f42144c196e19d7d497085b51d0f4cd52c (patch) | |
| tree | 38ab65d17c3613371cc9ff487d6b140724513004 /src/soc/intel/cannonlake | |
| parent | 04e49425ec1f1aaccf4695ab01d0f0181d5923ae (diff) | |
vc/amd/agesa: Fix out of bounds read
ByteLane is used unitialized from prior for statement,
creating a potential out-of-bound read of RxOrig[MaxByteLanes].
PassTestRxEnDly[MaxByteLanes] never appears as rvalue; all for
loops have ByteLane < MaxByteLanes exit condition.
Change-Id: Icd18a146aba6b6120d37518d8c40c7efbc05afa3
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241804
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
0 files changed, 0 insertions, 0 deletions