diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2020-06-04 19:57:54 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-08 19:07:53 +0000 |
| commit | d6161d46ff9563154f5c46509c0498ed11b16607 (patch) | |
| tree | 71f1e32abe94b01b339ad62244ae6e0c68588540 /src/soc/intel/cannonlake | |
| parent | 9455474f1b557cd93383a47c8debf1c60bff6063 (diff) | |
soc/amd/picasso: establish full early caching memory map
The PSP does the memory training and setting up of MSRs for
TOP_MEM and TOM2. Set caching up for all the DRAM areas:
Enable WB caching for 1MiB->TOP_MEM, 4GiB->TOM2.
Enable WC caching fro 0->1MiB except 0xa0000->0xc0000.
BUG=b:155426691
Change-Id: I83916a220ea4016d4438dd4fb5be82dec5506f80
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/intel/cannonlake')
0 files changed, 0 insertions, 0 deletions