soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroring

Drop the old, redundant code for mirroring LPC registers to DMI and make
use of the new common code.

Select the new Kconfig option for LPC DMI mirroring by the option
SOC_INTEL_COMMON_PCH_BASE, which is selected by platforms starting with
SPT, except APL and Xeon-SP. For Xeon-SP, select DMI and the new Kconfig
directly.

APL, even though it's younger than SPT, does not need mirroring.

Test: Set LGMR address by calling `lpc_open_mmio_window` and check that
      both the PCI cfg and DMI LGMR register get written correctly.

Tested successfully on clevo/cml-u.

Change-Id: Ibd834f1474d986646bcebb754a17db97831a651f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

2 files changed, 2 insertions, 39 deletions

diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index f4208450b3..a618988116 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -38,9 +38,6 @@
 #define PCR_DMI_PMBASEA		0x27AC
 #define PCR_DMI_PMBASEC		0x27B0
 
-#define PCR_DMI_LPCIOD		0x2770
-#define PCR_DMI_LPCIOE		0x2774
-
 static uint32_t get_pmc_reg_base(void)
 {
 	if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
@@ -140,19 +137,8 @@ void pch_early_iorange_init(void)
 		lpc_io_setup_comm_a_b();
 
 	/* IO Decode Enable */
-	if (pch_check_decode_enable() == 0) {
-		io_enables = lpc_enable_fixed_io_ranges(io_enables);
-		/*
-		 * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same
-		 * value programmed in LPC PCI offset 82h.
-		 */
-		pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
-		/*
-		 * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
-		 * value programmed in LPC PCI offset 80h.
-		 */
-		pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
-	}
+	if (pch_check_decode_enable() == 0)
+		lpc_enable_fixed_io_ranges(io_enables);
 
 	/* Program generic IO Decode Range */
 	pch_enable_lpc();
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index b03f21e2a2..20704e5bc6 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -9,7 +9,6 @@
 #include <arch/ioapic.h>
 #include <intelblocks/itss.h>
 #include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
 #include <soc/iomap.h>
 #include <soc/irq.h>
 #include <soc/lpc.h>
@@ -28,28 +27,7 @@ void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
 	gen_io_dec[3] = config->gen4_dec;
 }
 
-void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
-{
-	/* Mirror these same settings in DMI PCR */
-	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
-	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
-	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
-	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
-}
-
 #if ENV_RAMSTAGE
-static void soc_mirror_dmi_pcr_io_dec(void)
-{
-	uint32_t io_dec_arr[] = {
-		pci_read_config32(PCH_DEV_LPC, LPC_GEN1_DEC),
-		pci_read_config32(PCH_DEV_LPC, LPC_GEN2_DEC),
-		pci_read_config32(PCH_DEV_LPC, LPC_GEN3_DEC),
-		pci_read_config32(PCH_DEV_LPC, LPC_GEN4_DEC),
-	};
-	/* Mirror these same settings in DMI PCR */
-	soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
-}
-
 void lpc_soc_init(struct device *dev)
 {
 	const config_t *config = dev->chip_info;
@@ -69,7 +47,6 @@ void lpc_soc_init(struct device *dev)
 	pch_pirq_init();
 	setup_i8259();
 	i8259_configure_irq_trigger(9, 1);
-	soc_mirror_dmi_pcr_io_dec();
 }
 
 /* Fill up LPC IO resource structure inside SoC directory */