diff options
author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/soc/intel/cannonlake | |
parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r-- | src/soc/intel/cannonlake/acpi.c | 6 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/acpi/scs.asl | 4 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/acpi/southbridge.asl | 2 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/bootblock/bootblock.c | 4 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/bootblock/cpu.c | 4 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/bootblock/pch.c | 2 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/chip.c | 4 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/chip.h | 4 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/cnl_memcfg_init.c | 2 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/cpu.c | 2 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 2 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/graphics.c | 2 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/include/soc/gpio.h | 2 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/include/soc/pmc.h | 2 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/include/soc/smm.h | 2 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/lpc.c | 2 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/memmap.c | 2 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 4 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/smihandler.c | 2 |
19 files changed, 27 insertions, 27 deletions
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 127d9c8b64..639f6c6f90 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -204,14 +204,14 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) + if (CONFIG(CONSOLE_CBMEM)) /* Update the mem console pointer. */ gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; } else diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 1806e75e87..cdfff911b8 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -112,7 +112,7 @@ Scope (\_SB.PCI0) { And (PMCR, 0xFFFC, PMCR) Store (PMCR, ^TEMP) -#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) +#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) /* Change pad mode to Native */ GPMO(SD_PWR_EN_PIN, 0x1) #endif @@ -126,7 +126,7 @@ Scope (\_SB.PCI0) { Or (PMCR, 0x0003, PMCR) Store (PMCR, ^TEMP) -#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) +#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) /* Change pad mode to GPIO control */ GPMO(SD_PWR_EN_PIN, 0x0) diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index ae8de6a1df..d9ff70b6bc 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -30,7 +30,7 @@ #include "scs.asl" /* GPIO controller */ -#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) #include "gpio_cnp_h.asl" #else #include "gpio.asl" diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 08a13ea860..5555969289 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -20,7 +20,7 @@ #include <soc/iomap.h> #include <soc/pch.h> -#if IS_ENABLED(CONFIG_FSP_CAR) +#if CONFIG(FSP_CAR) #include <FsptUpd.h> const FSPT_UPD temp_ram_init_params = { @@ -53,7 +53,7 @@ void bootblock_soc_early_init(void) bootblock_pch_early_init(); bootblock_cpu_init(); pch_early_iorange_init(); - if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); } diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c index 3ebe1e48e6..f60f319999 100644 --- a/src/soc/intel/cannonlake/bootblock/cpu.c +++ b/src/soc/intel/cannonlake/bootblock/cpu.c @@ -21,7 +21,7 @@ void bootblock_cpu_init(void) { /* Temporarily cache the memory-mapped boot media. */ - if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) && - IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) + if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) && + CONFIG(BOOT_DEVICE_SPI_FLASH)) fast_spi_cache_bios_region(); } diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 018ccfc467..1c7fd7f082 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -162,7 +162,7 @@ void pch_early_iorange_init(void) LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; /* IO Decode Range */ - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + if (CONFIG(DRIVERS_UART_8250IO)) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index a643954a91..993e7f3d4a 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -29,7 +29,7 @@ #include <soc/ramstage.h> #include <string.h> -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -195,7 +195,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, - #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, #endif }; diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index ab7c765043..3e4bafc322 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -30,7 +30,7 @@ #include <soc/serialio.h> #include <soc/usb.h> #include <soc/vr_config.h> -#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) #include <soc/gpio_defs_cnp_h.h> #else #include <soc/gpio_defs.h> @@ -107,7 +107,7 @@ struct soc_intel_cannonlake_config { enum { SaGv_Disabled, SaGv_FixedLow, -#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE) +#if !CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) SaGv_FixedMid, #endif SaGv_FixedHigh, diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index e97b5711e8..db001b82ae 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -90,7 +90,7 @@ static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, die("spd.bin not found or incorrect index\n"); spd_data_len = region_device_sz(&spd_rdev); /* Memory leak is ok since we have memory mapped boot media */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); meminit_spd_data(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr); } diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 19ff171eb8..6bedb81390 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -497,7 +497,7 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) * have this check, where CNL CPU die is not based on KBL CPU * so skip this check for CNL. */ - if (!IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE)) + if (!CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)) return 0; /* diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 1ebde35e05..318b8a25ae 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -213,7 +213,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } else { params->ScsSdCardEnabled = dev->enabled; params->SdCardPowerEnableActiveHigh = - IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); + CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); } dev = dev_find_slot(0, PCH_DEVFN_UFS); diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 2b3c9007a4..015220d249 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -54,7 +54,7 @@ void graphics_soc_init(struct device *dev) * In case of non-FSP solution, SoC need to select VGA_ROM_RUN * Kconfig to perform GFX initialization through VGA OpRom. */ - if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT)) + if (CONFIG(INTEL_GMA_ADD_VBT)) return; /* IGD needs to Bus Master */ diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h index 718372ddc1..e7056ebcec 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio.h +++ b/src/soc/intel/cannonlake/include/soc/gpio.h @@ -16,7 +16,7 @@ #ifndef _SOC_CANNONLAKE_GPIO_H_ #define _SOC_CANNONLAKE_GPIO_H_ -#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) #include <soc/gpio_defs_cnp_h.h> #define CROS_GPIO_DEVICE_NAME "INT3450:00" #else diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index c3957d39c8..95cca65ab2 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -116,7 +116,7 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) -#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) #define PMC_GPP_A 0x0 #define PMC_GPP_B 0x1 #define PMC_GPP_C 0x2 diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index 9121ac3031..e38c3381d8 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -50,7 +50,7 @@ struct smm_relocation_params { /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 5dffb8197e..7c6025cb75 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -227,7 +227,7 @@ void lpc_soc_init(struct device *dev) lpc_enable_pci_clk_cntl(); /* Set LPC Serial IRQ mode */ - if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) + if (CONFIG(SERIRQ_CONTINUOUS_MODE)) lpc_set_serirq_mode(SERIRQ_CONTINUOUS); else lpc_set_serirq_mode(SERIRQ_QUIET); diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 8ffda2a57b..b2dd26dcf0 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -147,7 +147,7 @@ static size_t calculate_traditional_mem_size(uintptr_t dram_base, traditional_mem_base -= sa_get_tseg_size(); /* Get DPR size */ - if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) + if (CONFIG(SA_ENABLE_DPR)) traditional_mem_base -= sa_get_dpr_size(); /* Traditional Area Size */ diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index b8b2c1798c..5597c4f230 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -34,7 +34,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; - if (IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)) + if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) m_cfg->UserBd = BOARD_TYPE_DESKTOP; else m_cfg->UserBd = BOARD_TYPE_ULT_ULX; @@ -53,7 +53,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->VmxEnable = 0; else m_cfg->VmxEnable = config->VmxEnable; -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE) +#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); #endif diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 5f9e0f82af..643fad645f 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -93,7 +93,7 @@ void smihandler_soc_at_finalize(void) void smihandler_soc_check_illegal_access(uint32_t tco_sts) { - if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM) + if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) && fast_spi_wpd_status())) return; |