diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-10 23:36:44 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:29:31 +0000 |
| commit | c8a649c08f92d4d2255626da4e1cd7a6d71469e7 (patch) | |
| tree | 14a899738d09b37030585aca3b59344595208e36 /src/soc/intel/cannonlake | |
| parent | 846b4941fee842bc359fa2b611cf0c3fc4f158b2 (diff) | |
src: Use of device_t is deprecated
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/pch.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/report_platform.c | 10 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/smihandler.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/smmrelocate.c | 2 |
4 files changed, 11 insertions, 10 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 8e4f7fd81e..dc70a4f6c7 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -52,7 +52,7 @@ static void enable_p2sbbar(void) { - device_t dev = PCH_DEV_P2SB; + pci_devfn_t dev = PCH_DEV_P2SB; /* Enable PCR Base address in PCH */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index c81e53435c..a2cd864cf3 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -69,12 +69,12 @@ static struct { { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" }, }; -static uint8_t get_dev_revision(device_t dev) +static uint8_t get_dev_revision(pci_devfn_t dev) { return pci_read_config8(dev, PCI_REVISION_ID); } -static uint16_t get_dev_id(device_t dev) +static uint16_t get_dev_id(pci_devfn_t dev) { return pci_read_config16(dev, PCI_DEVICE_ID); } @@ -140,7 +140,7 @@ static void report_cpu_info(void) static void report_mch_info(void) { int i; - device_t dev = SA_DEV_ROOT; + pci_devfn_t dev = SA_DEV_ROOT; uint16_t mchid = get_dev_id(dev); uint8_t mch_revision = get_dev_revision(dev); const char *mch_type = "Unknown"; @@ -159,7 +159,7 @@ static void report_mch_info(void) static void report_pch_info(void) { int i; - device_t dev = PCH_DEV_LPC; + pci_devfn_t dev = PCH_DEV_LPC; uint16_t lpcid = get_dev_id(dev); const char *pch_type = "Unknown"; @@ -176,7 +176,7 @@ static void report_pch_info(void) static void report_igd_info(void) { int i; - device_t dev = SA_DEV_IGD; + pci_devfn_t dev = SA_DEV_IGD; uint16_t igdid = get_dev_id(dev); const char *igd_type = "Unknown"; diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index ba010aaa60..0ecc66df02 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -35,7 +35,8 @@ const struct smm_save_state_ops *get_smm_save_state_ops(void) return &em64t101_smm_ops; } -static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask) +static void pch_configure_endpoints(pci_devfn_t dev, int epmask_id, + uint32_t mask) { uint32_t reg32; @@ -43,7 +44,7 @@ static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask) pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask); } -static void disable_sideband_access(device_t dev) +static void disable_sideband_access(pci_devfn_t dev) { u8 reg8; uint32_t mask; @@ -60,7 +61,7 @@ static void disable_sideband_access(device_t dev) static void pch_disable_heci(void) { - device_t dev = PCH_DEV_P2SB; + pci_devfn_t dev = PCH_DEV_P2SB; struct pcr_sbi_msg msg = { .pid = PID_CSME0, .offset = 0, diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 83330e6ba6..3c60ef2b34 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -255,7 +255,7 @@ static void setup_ied_area(struct smm_relocation_params *params) void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); |