soc/intel/*: drop incomplete and unneeded check for DMI SRLOCK

Before enabling IO decode ranges, current code checks if the DMI SRLOCK
is set to prevent inconsistencies between LPC PCI cfg registers and LPC
DMI registers, when the latter are locked.

DMI SRLOCK only applies to PCHs with on-package DMI, but not to PCH-H,
PCH-S and others with discrete PCH packages. So this check is at least
incomplete.

Further, the lock gets applied by FSP and gets reset on a warm reset.
Thus, there is no case where the lock would be already set at the
places where the DMI registers get written currently.

Drop the checks for the reasons mentioned above.

Change-Id: I59554ce96bce7f7d1a4ba9b098be9e8466c68eac
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49885
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 1 insertions, 16 deletions

diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index a618988116..51f8fb59f6 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -113,20 +113,6 @@ static void soc_config_acpibase(void)
 	}
 }
 
-static int pch_check_decode_enable(void)
-{
-	uint32_t dmi_control;
-
-	/*
-	 * This cycle decoding is only allowed to set when
-	 * DMICTL.SRLOCK is 0.
-	 */
-	dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
-	if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
-		return -1;
-	return 0;
-}
-
 void pch_early_iorange_init(void)
 {
 	uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
@@ -137,8 +123,7 @@ void pch_early_iorange_init(void)
 		lpc_io_setup_comm_a_b();
 
 	/* IO Decode Enable */
-	if (pch_check_decode_enable() == 0)
-		lpc_enable_fixed_io_ranges(io_enables);
+	lpc_enable_fixed_io_ranges(io_enables);
 
 	/* Program generic IO Decode Range */
 	pch_enable_lpc();