diff options
| author | John Zhao <john.zhao@intel.com> | 2021-03-02 09:31:15 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-15 06:30:52 +0000 |
| commit | f3a8bf13cbfc43e45f0bb6e451608a082b59f7bf (patch) | |
| tree | 49ed6cbacfc2f3dc43ca075c3a093d8ebea10996 /src/soc/intel/cannonlake/uart.c | |
| parent | 80273918d5972157e6576ac983a14244d6074af1 (diff) | |
soc/intel/alderlake: Drop 100ms delay and do not poll Link Active
Drop the 100ms delay in the _PS0 method because kernel already adds this
100ms. This change also drops polling TBT PCIe root ports Link Active
State because this scheme is not applicable for SW CM.
BUG=None
TEST=Built Alderlake coreboot image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/uart.c')
0 files changed, 0 insertions, 0 deletions