diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-07-11 12:33:22 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-15 20:21:22 +0000 |
| commit | 8465a81e81dfb2ed1fc24b9cf053b09d86fa5163 (patch) | |
| tree | ff6a331f40c5887ee583359adb4a643905fc1e45 /src/soc/intel/cannonlake/romstage | |
| parent | e2ef3cf8e3ba130fe7388c905fc06aa3ff8b0506 (diff) | |
soc/intel/cannonlake: Add postcar stage support
Initialize postcar frame once finish FSP memoryinit
This patch was merged too early and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20534
Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20688
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/romstage')
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/romstage.c | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 7484b8d91d..2f8617e4cf 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -14,6 +14,7 @@ */ #include <arch/io.h> +#include <cpu/x86/mtrr.h> #include <cbmem.h> #include <console/console.h> #include <fsp/util.h> @@ -25,6 +26,8 @@ asmlinkage void car_stage_entry(void) { bool s3wake; + struct postcar_frame pcf; + uintptr_t top_of_ram; struct chipset_power_state *ps; console_init(); @@ -36,7 +39,25 @@ asmlinkage void car_stage_entry(void) timestamp_add_now(TS_START_ROMSTAGE); s3wake = ps->prev_sleep_state == ACPI_S3; fsp_memory_init(s3wake); - die("Get out from FSP memoryinit. \n"); + if (postcar_frame_init(&pcf, 1 * KiB)) + die("Unable to initialize postcar frame.\n"); + + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + top_of_ram -= 16*MiB; + postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1, + CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + run_postcar_phase(&pcf); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |