diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-11-30 10:10:59 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-20 16:39:19 +0000 |
| commit | 22d20d6f1450e0c6cc86f3903b7546f4e0b706cc (patch) | |
| tree | 689e004ce2a29bbdd285ed59dc25f0fd5d706675 /src/soc/intel/cannonlake/romstage | |
| parent | 1731a33e322e3760de2ffb5349923a592ebe97ac (diff) | |
soc/intel/cannonlake: Tell FSPM UART port number
Cannonlake FSP will send debug message on selected UART port, use same
coreboot UART debug port to FSP.
TEST=Boot up with board have UART port 0 and can see the print of FSP
Change-Id: Id72e459d2fbb1f16b005d22fac66667086880384
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/romstage')
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/romstage.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 94b54a66d3..8b3794f4e9 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -92,6 +92,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable Cpu Ratio Override temporary. */ m_cfg->CpuRatio = 0; + m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |