soc/intel/cannonlake: Refactor pch_early_init() code

This patch keeps required pch_early_init() function like ABASE programming,
GPE and RTC init into bootblock and moves remaining functions like TCO
configuration and SMBus init into romstage/pch.c in order to maintain only
required chipset programming for bootblock and verstage.

Rename the pch_init function to bootblock_pch_init and romstage_pch_init
according to the stage it is defined in.

TEST=Able to build and boot hatch successfully.

Change-Id: Idf7b04edc3fce147f7857561ce7d5b0cd05f43fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

1 files changed, 27 insertions, 0 deletions

diff --git a/src/soc/intel/cannonlake/romstage/pch.c b/src/soc/intel/cannonlake/romstage/pch.c
new file mode 100644
index 0000000000..8e783da6f9
--- /dev/null
+++ b/src/soc/intel/cannonlake/romstage/pch.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/smbus.h>
+#include <intelblocks/tco.h>
+#include <soc/romstage.h>
+
+void romstage_pch_init(void)
+{
+	/* Program TCO_BASE_ADDRESS and TCO Timer Halt */
+	tco_configure();
+
+	/* Program SMBUS_BASE_ADDRESS and enable it */
+	smbus_common_init();
+}