diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2019-03-27 14:16:01 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-27 09:20:10 +0000 |
| commit | 39f9fbc57aeb60e65ec42d370d7ab76c0a4584d6 (patch) | |
| tree | 921bdd4c46d8f4a0e6da5eab6c797e2fd5a452a2 /src/soc/intel/cannonlake/romstage/fsp_params.c | |
| parent | 9bc9da9d7e32a73f7c051327a77ed6ab445a1e0b (diff) | |
mb/mainboard/google/hatch/variants: Set tcc_offset value
Set tcc_offset value to 10C. It configures the Thermal Control Circuit (TCC)
activation value to 90C. This prevents any abrupt thermal shutdown by taking
early thermal throttling action when CPU temperature goes above 90C.
Change-Id: Ifee0fcc326530622b04e60af0f3b9cb9e3aea7ea
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31984
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/romstage/fsp_params.c')
0 files changed, 0 insertions, 0 deletions