diff options
| author | Usha P <usha.p@intel.com> | 2019-11-28 10:05:45 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-26 10:44:17 +0000 |
| commit | 33ff4cc137e501b14859bc67cc7e85dd60a863cc (patch) | |
| tree | 213e74f46592f0a1c029667cb339c80b0561e9ba /src/soc/intel/cannonlake/romstage/Makefile.inc | |
| parent | 5395123b849da143d9621b67a6837defe9501acf (diff) | |
soc/intel/cannonlake: Refactor pch_early_init() code
This patch keeps required pch_early_init() function like ABASE programming,
GPE and RTC init into bootblock and moves remaining functions like TCO
configuration and SMBus init into romstage/pch.c in order to maintain only
required chipset programming for bootblock and verstage.
Rename the pch_init function to bootblock_pch_init and romstage_pch_init
according to the stage it is defined in.
TEST=Able to build and boot hatch successfully.
Change-Id: Idf7b04edc3fce147f7857561ce7d5b0cd05f43fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/cannonlake/romstage/Makefile.inc')
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc index 33d9629e1d..ff3d73dee0 100644 --- a/src/soc/intel/cannonlake/romstage/Makefile.inc +++ b/src/soc/intel/cannonlake/romstage/Makefile.inc @@ -17,3 +17,4 @@ romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += fsp_params.c romstage-y += systemagent.c +romstage-y += pch.c |