diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-10-09 18:39:30 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-19 19:48:43 +0000 |
| commit | e7a1e7d3c49e980774985f3f6fae697dcb129420 (patch) | |
| tree | 2d801591554cc48950c343f94467cef6f8ebcef1 /src/soc/intel/cannonlake/reset.c | |
| parent | ed1694157c4f14d4ce60e7c053ea044aca6777fb (diff) | |
soc/intel/cannonlake: Fix HECI error on reset
Move HECI init from bootblock to romstage, the HECI bar saved by
CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage
will be read back from PCI. Also add fail safe option to reset in case
of HECI command not successful.
TEST= Force global reset from FSP and read back HECI bar in debug print.
Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/reset.c')
| -rw-r--r-- | src/soc/intel/cannonlake/reset.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index ca82bd6ac4..8192e89029 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -16,10 +16,12 @@ #include <compiler.h> #include <console/console.h> #include <intelblocks/cse.h> +#include <intelblocks/pmclib.h> #include <fsp/util.h> #include <reset.h> #include <string.h> #include <timer.h> +#include <soc/pci_devs.h> /* Reset Request */ #define MKHI_GLOBAL_RESET 0x0b @@ -82,10 +84,9 @@ void do_global_reset(void) { /* Ask CSE to do the global reset */ send_heci_reset_message(); - /* - * TODO: Presumbily we shouldn't return. But if we did, fallback to - * alternative way of triggered global reset provided by pmclib. - */ + /* global reset if CSE fail to reset */ + pmc_global_reset_enable(1); + hard_reset(); } void chipset_handle_reset(uint32_t status) |