diff options
author | Lijian Zhao <lijian.zhao@intel.com> | 2017-09-14 14:51:12 -0700 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-03 20:23:41 +0000 |
commit | f0eb99996d0baa7b0c09027f542a17d01c570a47 (patch) | |
tree | 747c6997e32e55677bc6c8e9a4007419f6724120 /src/soc/intel/cannonlake/memmap.c | |
parent | a515849259f71eb92d5465b6bcd9957b73db1889 (diff) |
soc/intel/cannonlake: Fill the SMI usage
Add SMM support for Cannonlake on top of common SMM, also include the
SMM relocate support.
Change-Id: I9aab141c528709b30804d327804c4031c59fcfff
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/memmap.c')
-rw-r--r-- | src/soc/intel/cannonlake/memmap.c | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 29f25f2693..0259cda7d6 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -23,9 +23,64 @@ #include <intelblocks/systemagent.h> #include <soc/bootblock.h> #include <soc/pci_devs.h> +#include <soc/smm.h> #include <soc/systemagent.h> #include <stdlib.h> +void smm_region(void **start, size_t *size) +{ + *start = (void *)sa_get_tseg_base(); + *size = sa_get_tseg_size(); +} + +/* + * Subregions within SMM + * +-------------------------+ BGSM + * | IED | IED_REGION_SIZE + * +-------------------------+ + * | External Stage Cache | SMM_RESERVED_SIZE + * +-------------------------+ + * | code and data | + * | (TSEG) | + * +-------------------------+ TSEG + */ +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + void *smm_base; + const size_t ied_size = CONFIG_IED_REGION_SIZE; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + smm_region(&smm_base, &sub_size); + sub_base = (uintptr_t)smm_base; + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= ied_size; + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - (ied_size + cache_size); + sub_size = cache_size; + break; + case SMM_SUBREGION_CHIPSET: + /* IED is at the top. */ + sub_base += sub_size - ied_size; + sub_size = ied_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} + static void *top_of_ram_register(void) { int num; |