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authorMichael Niewöhner <foss@mniewoehner.de>2021-01-23 13:57:03 +0100
committerNico Huber <nico.h@gmx.de>2021-01-24 14:03:33 +0000
commit89fe2f34b48dfa053de4c82771f078a136ffff20 (patch)
treee83c0f9bfa3ca5af7449184fa5dfb043d9b2d53c /src/soc/intel/cannonlake/lpc.c
parentd0d528a92a3605accabc1bfe6ddd35fab232c29a (diff)
soc/intel/cnl: use Kconfig to determine PCH type
We already know the PCH type at build time, so there is no need to do runtime detection. Thus, use Kconfig and drop `get_pch_series()`. Change-Id: I470871af5f5954e91a8135fddf4a2297a514d740 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49874 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/lpc.c')
-rw-r--r--src/soc/intel/cannonlake/lpc.c25
1 files changed, 0 insertions, 25 deletions
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index 26bda70845..b03f21e2a2 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -37,31 +37,6 @@ void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
}
-uint8_t get_pch_series(void)
-{
- uint16_t lpc_did_hi_byte;
- uint8_t pch_series = PCH_UNKNOWN_SERIES;
- /*
- * Fetch upper 8 bits on LPC device ID to determine PCH type
- * Adding 1 to the offset to fetch upper 8 bits
- */
- lpc_did_hi_byte = pci_read_config8(PCH_DEV_LPC, PCI_DEVICE_ID + 1);
-
- switch (lpc_did_hi_byte) {
- case 0x9D: /* CNL-LP */
- case 0x02: /* CML-LP */
- pch_series = PCH_LP;
- break;
- case 0xA3: /* CFL-H */
- case 0x06: /* CML-H */
- pch_series = PCH_H;
- break;
- default:
- break;
- }
- return pch_series;
-}
-
#if ENV_RAMSTAGE
static void soc_mirror_dmi_pcr_io_dec(void)
{