soc/intel/cannonlake: Fill the SMI usage

Add SMM support for Cannonlake on top of common SMM, also include the
SMM relocate support.

Change-Id: I9aab141c528709b30804d327804c4031c59fcfff
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2 files changed, 72 insertions, 10 deletions

diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h
index 931281a5c9..6617d7fa53 100644
--- a/src/soc/intel/cannonlake/include/soc/msr.h
+++ b/src/soc/intel/cannonlake/include/soc/msr.h
@@ -20,22 +20,13 @@
 #include <intelblocks/msr.h>
 
 #define MSR_PIC_MSG_CONTROL		0x2e
-#define MSR_BIOS_UPGD_TRIG		0x7a
 #define IA32_THERM_INTERRUPT		0x19b
 #define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
 #define  ENERGY_POLICY_PERFORMANCE	0
 #define  ENERGY_POLICY_NORMAL		6
 #define  ENERGY_POLICY_POWERSAVE	15
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
-#define PRMRR_PHYS_BASE_MSR		0x1f4
-#define IA32_PLATFORM_DCA_CAP		0x1f8
-#define MSR_LT_LOCK_MEMORY		0x2e7
-#define MSR_SGX_OWNEREPOCH0		0x300
-#define MSR_SGX_OWNEREPOCH1		0x301
-#define MSR_VR_CURRENT_CONFIG		0x601
-#define MSR_VR_MISC_CONFIG		0x603
+#define IA32_PLATFORM_DCA_CAP		0x1f9
 #define MSR_VR_MISC_CONFIG2		0x636
-#define MSR_PP0_POWER_LIMIT		0x638
-#define MSR_PP1_POWER_LIMIT		0x640
 
 #endif
diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h
new file mode 100644
index 0000000000..9121ac3031
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/smm.h
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_SMM_H_
+#define _SOC_SMM_H_
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <fsp/memmap.h>
+#include <soc/gpio.h>
+
+struct ied_header {
+	char signature[10];
+	u32 size;
+	u8 reserved[34];
+} __packed;
+
+struct smm_relocation_params {
+	u32 smram_base;
+	u32 smram_size;
+	u32 ied_base;
+	u32 ied_size;
+	msr_t smrr_base;
+	msr_t smrr_mask;
+	msr_t emrr_base;
+	msr_t emrr_mask;
+	msr_t uncore_emrr_base;
+	msr_t uncore_emrr_mask;
+	/*
+	 * The smm_save_state_in_msrs field indicates if SMM save state
+	 * locations live in MSRs. This indicates to the CPUs how to adjust
+	 * the SMMBASE and IEDBASE
+	 */
+	int smm_save_state_in_msrs;
+};
+
+/* Mainboard handler for eSPI SMIs */
+void mainboard_smi_espi_handler(void);
+
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
+				uintptr_t staggered_smbase);
+void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
+		size_t *smm_save_state_size);
+void smm_initialize(void);
+void smm_relocate(void);
+
+#else	/* CONFIG_HAVE_SMI_HANDLER */
+static inline void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
+				uintptr_t staggered_smbase) {}
+static inline void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
+		size_t *smm_save_state_size) {}
+static inline void smm_initialize(void) {}
+
+static inline void smm_relocate(void) {}
+#endif	/* CONFIG_HAVE_SMI_HANDLER */
+
+#endif