diff options
author | Lijian Zhao <lijian.zhao@intel.com> | 2017-10-09 18:39:30 -0700 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-19 19:48:43 +0000 |
commit | e7a1e7d3c49e980774985f3f6fae697dcb129420 (patch) | |
tree | 2d801591554cc48950c343f94467cef6f8ebcef1 /src/soc/intel/cannonlake/include | |
parent | ed1694157c4f14d4ce60e7c053ea044aca6777fb (diff) |
soc/intel/cannonlake: Fix HECI error on reset
Move HECI init from bootblock to romstage, the HECI bar saved by
CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage
will be read back from PCI. Also add fail safe option to reset in case
of HECI command not successful.
TEST= Force global reset from FSP and read back HECI bar in debug print.
Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
-rw-r--r-- | src/soc/intel/cannonlake/include/soc/iomap.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index add5ee8a75..22430f055b 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -63,7 +63,7 @@ #define GPIO_BASE_SIZE 0x10000 -#define HECI1_BASE_ADDRESS 0xFEDA2000 +#define HECI1_BASE_ADDRESS 0xfeda2000 /* PTT registers */ #define PTT_TXT_BASE_ADDRESS 0xfed30800 |