diff options
| author | John Zhao <john.zhao@intel.com> | 2019-03-15 16:54:27 -0700 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-04-18 10:15:55 +0000 |
| commit | db3f0e3ebd8364d3cd46130743f38ff8425299f8 (patch) | |
| tree | a8c538b6980ede915d85226fb1fdf980d814ad88 /src/soc/intel/cannonlake/include | |
| parent | 45d4b17f5e05cd493f19e69900a38ac805eb63b5 (diff) | |
soc/intel/cnl: Generate DMAR ACPI table
The platform supports Virtualization Technology for Directed I/O.
Generate DMAR acpi table if VT-d feature is enabled.
BUG=b:130351429
TEST=Booted to kernel and verified the DMAR table contents.
Change-Id: I4e1ee5244c67affb13947436d81628c5dc665c9e
Signed-off-by: John Zhao <john.zhao@intel.com>
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/iomap.h | 9 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/systemagent.h | 27 |
2 files changed, 36 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index ed9b29ffee..100bd11356 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -52,6 +52,15 @@ #define EDRAM_BASE_ADDRESS 0xfed80000 #define EDRAM_BASE_SIZE 0x4000 +#define GFXVT_BASE_ADDRESS 0xfed90000 +#define GFXVT_BASE_SIZE 0x1000 + +#define IPUVT_BASE_ADDRESS 0xfed92000 +#define IPUVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000 +#define VTVC0_BASE_SIZE 0x1000 + #define REG_BASE_ADDRESS 0xfc000000 #define REG_BASE_SIZE 0x1000 diff --git a/src/soc/intel/cannonlake/include/soc/systemagent.h b/src/soc/intel/cannonlake/include/soc/systemagent.h index da83c381a0..3bda9e8d59 100644 --- a/src/soc/intel/cannonlake/include/soc/systemagent.h +++ b/src/soc/intel/cannonlake/include/soc/systemagent.h @@ -30,10 +30,17 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) #define BIOS_RESET_CPL 0x5da8 +#define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 +#define IPUVTBAR 0x7880 +#define VTVC0BAR 0x5410 #define REGBAR 0x5420 +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK 0x7ffffff000ull #define MCH_PKG_POWER_LIMIT_LO 0x59a0 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 @@ -43,4 +50,24 @@ #define IMRBASE 0x6A40 #define IMRLIMIT 0x6A48 +#if CONFIG(SOC_INTEL_COFFEELAKE) || CONFIG(SOC_INTEL_WHISKEYLAKE) \ + || CONFIG(SOC_INTEL_COMETLAKE) +static const struct sa_mmio_descriptor soc_vtd_resources[] = { + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +}; +#else +static const struct sa_mmio_descriptor soc_vtd_resources[] = { + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +}; +#endif + +#define V_P2SB_CFG_IBDF_BUS 0 +#define V_P2SB_CFG_IBDF_DEV 30 +#define V_P2SB_CFG_IBDF_FUNC 7 +#define V_P2SB_CFG_HBDF_BUS 0 +#define V_P2SB_CFG_HBDF_DEV 30 +#define V_P2SB_CFG_HBDF_FUNC 6 #endif |