aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/cannonlake/include
diff options
context:
space:
mode:
authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2019-01-08 19:52:54 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-01-16 12:44:17 +0000
commitc896e92eaad8e255c1cef65b9da2367742a61e5f (patch)
tree4cc223ff714a75c4355c3fa5ce8c81261181612d /src/soc/intel/cannonlake/include
parente97e90959c6d7424911bfbc0096d6054cb27c434 (diff)
soc/intel/cannonlake: Add processor power limits control support
Add processor power limits control support to configure values. BRANCH=None BUG=b:122343940 TEST=Built and tested on Arcada system Change-Id: I5990dc05b51481a0074855914cef20cf07378cde Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
-rw-r--r--src/soc/intel/cannonlake/include/soc/msr.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h
index e3bd5f6ebc..63595f353f 100644
--- a/src/soc/intel/cannonlake/include/soc/msr.h
+++ b/src/soc/intel/cannonlake/include/soc/msr.h
@@ -20,6 +20,9 @@
#include <intelblocks/msr.h>
#define MSR_PIC_MSG_CONTROL 0x2e
+#define MSR_VR_CURRENT_CONFIG 0x601
+#define MSR_PL3_CONTROL 0x615
#define MSR_VR_MISC_CONFIG2 0x636
+#define MSR_PLATFORM_POWER_LIMIT 0x65c
#endif