diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-10-12 17:59:02 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-18 01:13:51 +0000 |
| commit | 47569cf3a9be5d42a75c932d4148fa20c2d8b475 (patch) | |
| tree | b5c04ad951389a26e1eab016f5856eeb94e3ca2b /src/soc/intel/cannonlake/include | |
| parent | d2cadc39f3894612ca7714d5a4712bd3c09f42de (diff) | |
soc/intel/cannonlake: Use EBDA area to store cbmem_top address
This patch uses BIOS EBDA area to store relevent details
like cbmem top during romstage after MRC init is done.
Also provide provision to use the same EBDA data across
various stages without reexecuting memory map algorithm.
BRANCH=none
BUG=b:63974384
TEST=Ensures HW based memmap algorithm is executing once in romstage
and store required data into EBDA for other stage to avoid redundant
calculation and get cbmem_top start from EBDA area.
Change-Id: I763ad8181396ea8d8c0d5cf088264791ba62dceb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/bootblock.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/ebda.h | 24 |
2 files changed, 24 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/bootblock.h b/src/soc/intel/cannonlake/include/soc/bootblock.h index fcef4ef358..2a6ca1fb15 100644 --- a/src/soc/intel/cannonlake/include/soc/bootblock.h +++ b/src/soc/intel/cannonlake/include/soc/bootblock.h @@ -27,6 +27,4 @@ void pch_early_init(void); void pch_early_iorange_init(void); void report_platform_info(void); -void clear_cbmem_top(void); - #endif diff --git a/src/soc/intel/cannonlake/include/soc/ebda.h b/src/soc/intel/cannonlake/include/soc/ebda.h new file mode 100644 index 0000000000..4cde5c0106 --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/ebda.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_EBDA_H +#define SOC_EBDA_H + +struct ebda_config { + uint32_t signature; /* 0x00 - EBDA signature */ + uint32_t tolum_base; /* 0x04 - coreboot memory start */ +}; + +#endif |