soc/intel/cannonlake: Add common ACPI support for CNL

Basic ACPI support for CNL on top of common ACPI, which will establish
a root of FADT table, fill MADT entry, create gnvs field, record wake
status and convert device names into DSDT dev definitions.

Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 58 insertions, 3 deletions

diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
index e9a5b89491..d4994e74e4 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
@@ -248,4 +248,5 @@
 
 #define NUM_GPIO_COM2_PADS	(GPD11 - GPD0 + 1)
 
+#define TOTAL_PADS		188
 #endif
diff --git a/src/soc/intel/cannonlake/include/soc/nvs.h b/src/soc/intel/cannonlake/include/soc/nvs.h
new file mode 100644
index 0000000000..aa5093d4ef
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/nvs.h
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_NVS_H_
+#define _SOC_NVS_H_
+
+#include <compiler.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+
+typedef struct global_nvs_t {
+	/* Miscellaneous */
+	u16	osys; /* 0x00 - 0x01 Operating System */
+	u8	smif; /* 0x02 - SMI function call ("TRAP") */
+	u8      pcnt; /* 0x03 - Processor Count */
+	u8	ppcm; /* 0x04 - Max PPC State */
+	u8	tlvl; /* 0x05 - Throttle Level Limit */
+	u8	lids; /* 0x06 - LID State */
+	u8	pwrs; /* 0x07 - AC Power State */
+	u32	cbmc; /* 0x08 - 0xb AC Power State */
+	u64	pm1i; /* 0x0c - 0x13 PM1 wake status bit */
+	u64	gpei; /* 0x14 - 0x1b GPE wake status bit */
+	u8	dpte; /* 0x1c - Enable DPTF */
+	u64	nhla; /* 0x1d - 0x24 NHLT Address */
+	u32	nhll; /* 0x25 - 0x28 NHLT Length */
+	u16	cid1; /* 0x29 - 0x2a Wifi Country Identifier */
+	u16	u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */
+	u16	u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */
+	u8	uior; /* 0x2f - UART debug controller init on S3 resume */
+	u8	unused[208];
+
+	/* ChromeOS specific (0x100 - 0xfff) */
+	chromeos_acpi_t chromeos;
+}  __packed global_nvs_t;
+
+
+#endif
diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h
index 58037bd488..378fac9139 100644
--- a/src/soc/intel/cannonlake/include/soc/pm.h
+++ b/src/soc/intel/cannonlake/include/soc/pm.h
@@ -140,6 +140,11 @@
 #define ENABLE_SMI_PARAMS \
 	(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)
 
+#define	PSS_RATIO_STEP		2
+#define	PSS_MAX_ENTRIES		8
+#define	PSS_LATENCY_TRANSITION	10
+#define	PSS_LATENCY_BUSMASTER	10
+
 struct chipset_power_state {
 	uint16_t pm1_sts;
 	uint16_t pm1_en;
@@ -154,9 +159,6 @@ struct chipset_power_state {
 	uint32_t prev_sleep_state;
 } __packed;
 
-/* Return the selected ACPI SCI IRQ */
-int acpi_sci_irq(void);
-
 /* Get base address PMC memory mapped registers. */
 uint8_t *pmc_mmio_regs(void);
 
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h
index b8e49c2286..69954db6ce 100644
--- a/src/soc/intel/cannonlake/include/soc/pmc.h
+++ b/src/soc/intel/cannonlake/include/soc/pmc.h
@@ -119,6 +119,8 @@
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)
 #define GBLRST_CAUSE1			0x1928
 
+#define IRQ_REG				ACTL
+#define SCI_IRQ_ADJUST			0
 #define ACTL				0x1BD8
 #define   PWRM_EN			(1 << 8)
 #define   ACPI_EN			(1 << 7)