diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-10-05 10:31:11 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-26 11:20:00 +0000 |
| commit | 0f5d7b9daf3b2c7a2991c62580c9db9c3e8ac953 (patch) | |
| tree | 08f09ecf8980eaf664f24501d54b91df26127ec8 /src/soc/intel/cannonlake/include | |
| parent | c308554c10a33c977657b627c880cde60a590eb4 (diff) | |
soc/intel/cannonlake: Add back PM TIMER EMULATION
ACPI PM timer emulation will be added back as default FSP stops TCO count
for power saving, which will also stop ACPI PM timer within PCH. CPU PM TIMER
EMULATION will help UEFI payload pass, instead of endless loop wait for
ACPI PM timer counter to increase.
BUG=N/A
TEST=Build and boot up fine with whiskey lake rvp board into UEFI shell.
Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28937
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/cpu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h index dfc7183910..1e3e2b4cb1 100644 --- a/src/soc/intel/cannonlake/include/soc/cpu.h +++ b/src/soc/intel/cannonlake/include/soc/cpu.h @@ -37,6 +37,9 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 +/* Common Timer Copy (CTC) frequency - 24MHz. */ +#define CTC_FREQ 24000000 + #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ |