soc/intel/cannonlake: Support different SPD read type for each slot

Also clean up cannonlake_memcfg_init.

The major changes include:
(1) Add enum 'mem_info_read_type' to spd_info.
(2) Add per-dimm-slot spd_info to cnl_mb_cfg.
(3) Setup memory config for each slot independently.
(4) Squash meminit_memcfg_spd().

BUG=chromium:960581, b:124990009
BRANCH=none
TEST=boot hatch, hatch_whl, and kohaku

Change-Id: I686a85996858204c20fd05ef24787a0487817c34
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32513
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 21 insertions, 17 deletions

diff --git a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h
index e602a33f78..d5f6c39f24 100644
--- a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h
+++ b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h
@@ -23,6 +23,9 @@
 /* Number of dq bits controlled per dqs */
 #define DQ_BITS_PER_DQS 8
 
+/* Number of memory DIMM slots available on Cannonlake board */
+#define NUM_DIMM_SLOT 4
+
 /*
  * Number of memory packages, where a "package" represents a 64-bit solution.
  */
@@ -40,17 +43,32 @@ struct spd_by_pointer {
 	uintptr_t spd_data_ptr;
 };
 
+enum mem_info_read_type {
+	NOT_EXISTING,	/* No memory in this slot */
+	READ_SMBUS,	/* Read on-module spd by SMBUS. */
+	READ_SPD_CBFS,	/* Find spd file in CBFS. */
+	READ_SPD_MEMPTR /* Find spd data from pointer. */
+};
+
 struct spd_info {
-	bool spd_by_index;
+	enum mem_info_read_type read_type;
 	union spd_data_by {
+		/* To read on-module spd when read_type is READ_SMBUS. */
+		uint8_t spd_smbus_address;
+
+		/* To identify spd file when read_type is READ_SPD_CBFS. */
 		int spd_index;
+
+		/* To find spd data when read_type is READ_SPD_MEMPTR. */
 		struct spd_by_pointer spd_data_ptr_info;
 	} spd_spec;
-	uint8_t spd_smbus_address[4];
 };
 
 /* Board-specific memory dq mapping information */
 struct cnl_mb_cfg {
+	/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
+	struct spd_info spd[NUM_DIMM_SLOT];
+
 	/*
 	 * For each channel, there are 6 sets of DQ byte mappings,
 	 * where each set has a package 0 and a package 1 value (package 0
@@ -107,26 +125,12 @@ struct cnl_mb_cfg {
 
 	/* Early Command Training Enabled */
 	uint8_t ect;
-
-	/*
-	 * Flags to indicate which channels are populated.  We
-	 * currently support single or dual channel configurations.
-	 * Set 1 to indicate that the channel is not populated Set 0
-	 * to indicate that the channel is populated.  For example,
-	 * dual channel memory configuration would have both
-	 * channel_empty[0] = 0 and channel_empty[1] = 0.  Note that
-	 * this flag is only used for soldered down DRAM where we get
-	 * SPD data from CBFS.  We need the value 0 to default to
-	 * populated in order to support existing boards.
-	 */
-	uint8_t channel_empty[2];
 };
 
 /*
  * Initialize default memory configurations for CannonLake.
  */
 void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg,
-			const struct cnl_mb_cfg *cnl_cfg,
-			const struct spd_info *spd);
+			    const struct cnl_mb_cfg *cnl_cfg);
 
 #endif /* _SOC_CANNONLAKE_MEMCFG_INIT_H_ */