diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-12-15 12:58:07 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-05 20:44:15 +0000 |
| commit | 031020e431f8d013108957b856da5ff5c7c596f3 (patch) | |
| tree | 59c31103dcb0ce1a0580840c4e6c9332b15abaaa /src/soc/intel/cannonlake/include | |
| parent | d6f3dd83dc7d8bb66e29c489e82d4736779d7b6f (diff) | |
soc/intel/cannonlake: Correct PMC/GPIO routing information
PMC and GPIO DWx definition is not identical, hence update that to
correct information. For cannonlake lp PCH, GPIO group C, group E and
group GPD is different for PMC GPIO_CFG and GPIO MISCCFG. Also add
function call to set up GPE routing in bootblock stage.
TEST=Boot up into OS, and manually check PMC GPE status
Change-Id: I1edb83edabc72e8a762b129cf51dcd936cd37ddf
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pmc.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 0276d46089..b794ede967 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -116,6 +116,16 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) +#define PMC_GPP_A 0x0 +#define PMC_GPP_B 0x1 +#define PMC_GPP_C 0xD +#define PMC_GPP_D 0x4 +#define PMC_GPP_E 0xE +#define PMC_GPP_F 0x5 +#define PMC_GPP_G 0x2 +#define PMC_GPP_H 0x6 +#define PMC_GPD 0xA + #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) #define GBLRST_CAUSE1 0x1928 |