soc/intel/cnl and mainboards: Drop `cnl_configure_pads()`

CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is
done") introduced a workaround in coreboot for `soc/intel/cannonlake`
platforms to save and restore GPIO configuration performed by
mainboard across call to FSP Silicon Init (FSP-S). This workaround was
required because FSP-S was configuring GPIOs differently than
mainboard resulting in boot and runtime issues because of
misconfigured GPIOs.

This issue has since been fixed in FSP (verified with FSP v1263 on
hatch). However, there were still 4 boards in coreboot using
`cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u
and system76/lemp9 were tested to ensure that this workaround is no
longer required.

This change drops the workaround using `cnl_configure_pads()` and
updates all mainboards to use `gpio_configure_pads()` instead.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Tested-by: Angel Pons <th3fanbus@gmail.com>
(Tested purism/librem_cnl)
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
(Tested clevo/cml-u which is similar to system76/lemp9)
Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 1 insertions, 1 deletions

diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h
index 9ffa8f1bc2..f204ca2510 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio.h
@@ -19,7 +19,7 @@
 
 #ifndef __ACPI__
 struct pad_config;
-void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads);
+
 /*
  * Routine to perform below operations:
  * 1. SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register