diff options
author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2019-09-23 20:59:38 +0530 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-09 19:19:46 +0000 |
commit | 8e4654527ef5fec658ca5aacad0612653d3dcf30 (patch) | |
tree | 5cf7d9519334074506d31e0e3fbc446457fe4463 /src/soc/intel/cannonlake/include | |
parent | 6d5f007813f6a2ffbdd6a633f31d207672eee2e1 (diff) |
soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoC
Below changes are implemented:
1. Move HFSTS1 register definition to SoC since HFSTS1 register definition
is specific to a SoC. Moving structure back to SoC specific to avoid
unnecessay SoC specific macros in the common code.
2. Define a set of APIs in common code since CSE operation modes and
working states are same across SoCs.
cse_is_hfs1_com_normal(void)
cse_is_hfs1_com_secover_mei_msg(void)
cse_is_hfs1_com_soft_temp_disable(void)
cse_is_hfs1_cws_normal(void)
3. Modify existing code to use callbacks to get data of me_hfs1 structure.
TEST=Build and Boot hatch, soraka, tglrvp, bobba and iclrvp boards.
Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
-rw-r--r-- | src/soc/intel/cannonlake/include/soc/me.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/me.h b/src/soc/intel/cannonlake/include/soc/me.h index 5b411d3621..041769b19a 100644 --- a/src/soc/intel/cannonlake/include/soc/me.h +++ b/src/soc/intel/cannonlake/include/soc/me.h @@ -16,6 +16,34 @@ #ifndef _CANNONLAKE_ME_H_ #define _CANNONLAKE_ME_H_ +/* ME Host Firmware Status register 1 */ +union me_hfsts1 { + u32 data; + struct { + u32 working_state: 4; + u32 mfg_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reset_count: 4; + u32 boot_options_present: 1; +#if CONFIG(SOC_INTEL_COMETLAKE) + u32 invoke_enhance_dbg_mode:1; +#else + u32 reserved0: 1; +#endif + u32 bist_test_state: 1; + u32 bist_reset_request: 1; + u32 current_power_source: 2; + u32 reserved1: 1; + u32 d0i3_support_valid: 1; + } __packed fields; +}; + void dump_me_status(void *unused); #endif /* _CANNONLAKE_ME_H_ */ |