diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-23 13:57:03 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-01-24 14:03:33 +0000 |
| commit | 89fe2f34b48dfa053de4c82771f078a136ffff20 (patch) | |
| tree | e83c0f9bfa3ca5af7449184fa5dfb043d9b2d53c /src/soc/intel/cannonlake/include | |
| parent | d0d528a92a3605accabc1bfe6ddd35fab232c29a (diff) | |
soc/intel/cnl: use Kconfig to determine PCH type
We already know the PCH type at build time, so there is no need to do
runtime detection. Thus, use Kconfig and drop `get_pch_series()`.
Change-Id: I470871af5f5954e91a8135fddf4a2297a514d740
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49874
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/lpc.h | 11 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pch.h | 4 |
2 files changed, 0 insertions, 15 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h index c52bc9f5ec..a510bc51a9 100644 --- a/src/soc/intel/cannonlake/include/soc/lpc.h +++ b/src/soc/intel/cannonlake/include/soc/lpc.h @@ -31,15 +31,4 @@ #define PCCTL 0xE0 /* PCI Clock Control */ #define CLKRUN_EN (1 << 0) -/* - * This function will help to differentiate between 2 PCH on single type of soc. - * Since same soc may have LP series pch or H series PCH, we need to - * differentiate by reading upper 8 bits of PCH device ids. - * - * Return: - * Return PCH_LP or PCH_H macro in case of respective device ID found. - * PCH_UNKNOWN_SERIES in case of invalid device ID. - */ -uint8_t get_pch_series(void); - #endif diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h index e4fd36de33..768655f758 100644 --- a/src/soc/intel/cannonlake/include/soc/pch.h +++ b/src/soc/intel/cannonlake/include/soc/pch.h @@ -3,10 +3,6 @@ #ifndef _SOC_CANNONLAKE_PCH_H_ #define _SOC_CANNONLAKE_PCH_H_ -#define PCH_H 1 -#define PCH_LP 2 -#define PCH_UNKNOWN_SERIES 0xFF - #define PCIE_CLK_NOTUSED 0xFF #define PCIE_CLK_LAN 0x70 #define PCIE_CLK_FREE 0x80 |