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authorSubrata Banik <subrata.banik@intel.com>2019-05-15 21:23:18 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-05-20 14:50:16 +0000
commit76a8f9e29f3cb6aa2e971957eec7fc05abaf50b8 (patch)
treecd1c89bb0a29d00daef14dcc9418f5931eeac128 /src/soc/intel/cannonlake/include
parentdd5fa024260bf6fd19c077d640c34e27b742115b (diff)
soc/intel/cannonlake: Make use of gpio_pm_configure()
Provide option in chip.h to set dynamic local clock gating setting. BUG=b:130764684 TEST=Able to build and boot CML. Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
-rw-r--r--src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h8
-rw-r--r--src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h7
2 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
index 59901440d9..698bd2a5c7 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
@@ -355,4 +355,12 @@
#define TOTAL_PADS 275
#define SD_PWR_EN_PIN GPP_A17
+
+#define COMM_0 0
+#define COMM_1 1
+#define COMM_2 2
+#define COMM_3 3
+#define COMM_4 4
+#define TOTAL_GPIO_COMM 5
+
#endif
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
index 1788e78989..5176ac734a 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
@@ -399,4 +399,11 @@
#define TOTAL_PADS (GPD11 + 1)
+#define COMM_0 0
+#define COMM_1 1
+#define COMM_2 2
+#define COMM_3 3
+#define COMM_4 4
+#define TOTAL_GPIO_COMM 5
+
#endif