diff options
| author | Furquan Shaikh <furquan@google.com> | 2019-07-06 23:05:23 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-07-07 07:53:33 +0000 |
| commit | b29da7f79e7cfb16f5d8b23057bd91df760f79d3 (patch) | |
| tree | bae25799dc40792c06487f534dcc5c57061c0513 /src/soc/intel/cannonlake/include | |
| parent | 451ef598e6d4caff5cb8d9d798bfbb2b6874f627 (diff) | |
soc/intel/{cannonlake,icelake}: Do not define PCH_DEV_PMC in ramstage
This change intentionally removes the definition of PCH_DEV_PMC from
ramstage to avoid silent errors. This device gets hidden from PCI bus
in FSP-S and hence dropped from the root bus by the resource
allocator. In order to avoid incorrect references to the device, avoid
defining it in ramstage where it known to return NULL.
BUG=b:136861224
Change-Id: I4f69470ec80c7127a2b604ed2b1f794f5a63e126
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34120
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pci_devs.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 46bc1bfa20..1bc028f194 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -187,7 +187,19 @@ #define PCH_DEVFN_TRACEHUB _PCH_DEVFN(LPC, 7) #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_P2SB _PCH_DEV(LPC, 1) + +#if !ENV_RAMSTAGE +/* + * PCH_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets + * hidden from PCI bus after call to FSP-S. This leads to resource allocator + * dropping it from the root bus as unused device. All references to PCH_DEV_PMC + * would then return NULL and can go unnoticed if not handled properly. Since, + * this device does not have any special chip config associated with it, it is + * okay to not provide the definition for it in ramstage. + */ #define PCH_DEV_PMC _PCH_DEV(LPC, 2) +#endif + #define PCH_DEV_HDA _PCH_DEV(LPC, 3) #define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) |