diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-23 22:05:36 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-04 00:10:38 +0000 |
| commit | 51f5ff6d27ccb9d4f7e5401fe1c093b173711bf9 (patch) | |
| tree | fd4934d7a2d0d5de594ee1e9f08d7d6e6fe1a393 /src/soc/intel/cannonlake/include | |
| parent | 14512f9a9be08d945830ddb6d0e48f4d6fc1635c (diff) | |
soc/intel/{skl,cnl}: add NMI_{EN,STS} registers
Add NMI_EN and NMI_STS registers, so they can be configured for using
NMI gpios.
References:
- CMP-LP: Intel doc# 615146-1.2
- CMP-H: Intel doc# 620855-002
- SPT-H: Intel doc# 332691-003
- SPT-LP: Intel doc# 334659-005
- CNP-H: Intel doc# 337868-002
Test: trigger NMI via gpio on Supermicro X11SSM-F did not work before
but now makes the Linux kernel complain about a NMI.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I4d57ae89423bdaacf84f0bb0282bbb1c9df94598
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48091
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/gpio_defs.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index e7769b5f31..c96a67d69d 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -236,6 +236,8 @@ #define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 +#define GPI_NMI_STS_0 0x1c0 +#define GPI_NMI_EN_0 0x1e0 #define PAD_CFG_BASE 0x600 #endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index bd68b04f9b..4f87459cc4 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -310,6 +310,8 @@ #define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 +#define GPI_NMI_STS_0 0x1c0 +#define GPI_NMI_EN_0 0x1e0 #define PAD_CFG_BASE 0x600 #endif |