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author | Tristan Corrick <tristan@corrick.kiwi> | 2018-12-17 22:10:21 +1300 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-03 18:11:54 +0000 |
commit | 334be3289d6ca16e806bd1e2aef87637cebb3122 (patch) | |
tree | e9e50ce6ab73cd5d146be5aa0f7f25b584ac3c7f /src/soc/intel/cannonlake/i2c.c | |
parent | 05b75241565ae91d0b8ee8b45eb2d8ac55291297 (diff) |
nb/intel/haswell: Add support for PEG
This means that any PCIe device placed in a PEG slot should now work.
During S3 resume, link training sometimes does not complete before
device enumeration. However, no tangible issues have been observed.
Fixing it would introduce a rather large delay in S3 resume.
There are a few minor shortcomings:
- Using PEG for display output is not yet supported.
- Only PEG2 is supported. An extra (unknown) training sequence is said to
be needed for PEG3.
- The ACPI _PRT method is not yet generated, so legacy interrupt routing
doesn't work for devices with multiple functions.
Tested on an ASRock H81M-HDS. Using a Radeon HD 6450 graphics card works
under GNU/Linux, with PRIME [1]. An x1 PCIe card was also tested in the
PEG slot, and it appears functional.
[1]: https://wiki.archlinux.org/index.php/PRIME
Change-Id: I786ecb6eccad8de89778af7e736ed664323e220e
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel/cannonlake/i2c.c')
0 files changed, 0 insertions, 0 deletions