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authorLijian Zhao <lijian.zhao@intel.com>2017-10-30 17:03:06 -0700
committerMartin Roth <martinroth@google.com>2017-11-04 00:42:00 +0000
commit9bb684a0ec1f3c1a276ec6d7a9e83b5b75aa6350 (patch)
tree288a50a5e9f2299834f4370185b415aee614d00c /src/soc/intel/cannonlake/i2c.c
parentf08ed7d790ade3f29680dc300b71cf95a694ce2a (diff)
soc/intel/cannonlake: Install common i2c
Add common i2c support for cannonlake. TEST=N/A Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22238 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/i2c.c')
-rw-r--r--src/soc/intel/cannonlake/i2c.c81
1 files changed, 81 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/i2c.c b/src/soc/intel/cannonlake/i2c.c
new file mode 100644
index 0000000000..b0c35238ee
--- /dev/null
+++ b/src/soc/intel/cannonlake/i2c.c
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <intelblocks/lpss_i2c.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include "chip.h"
+
+const struct lpss_i2c_bus_config *i2c_get_soc_cfg(unsigned int bus,
+ const struct device *dev)
+{
+ const struct soc_intel_cannonlake_config *config;
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
+ __func__);
+ return NULL;
+ }
+
+ config = dev->chip_info;
+
+ return &config->i2c[bus];
+}
+
+uintptr_t i2c_get_soc_early_base(unsigned int bus)
+{
+ return EARLY_I2C_BASE(bus);
+}
+
+int i2c_soc_devfn_to_bus(unsigned int devfn)
+{
+ switch (devfn) {
+ case PCH_DEVFN_I2C0:
+ return 0;
+ case PCH_DEVFN_I2C1:
+ return 1;
+ case PCH_DEVFN_I2C2:
+ return 2;
+ case PCH_DEVFN_I2C3:
+ return 3;
+ case PCH_DEVFN_I2C4:
+ return 4;
+ case PCH_DEVFN_I2C5:
+ return 5;
+ }
+ return -1;
+}
+
+int i2c_soc_bus_to_devfn(unsigned int bus)
+{
+ switch (bus) {
+ case 0:
+ return PCH_DEVFN_I2C0;
+ case 1:
+ return PCH_DEVFN_I2C1;
+ case 2:
+ return PCH_DEVFN_I2C2;
+ case 3:
+ return PCH_DEVFN_I2C3;
+ case 4:
+ return PCH_DEVFN_I2C4;
+ case 5:
+ return PCH_DEVFN_I2C5;
+ }
+ return -1;
+}