soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions

- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities.

- Add gpio pin definitions for CNP-H and related changes.

- Add gpio device name, host software ownership reg offset for CNP-H.

BUG: none
TEST: build and flash, boot to windows and yocto os on both CFL RVP8 &
      RVP11 and verify power management, IO device functionalities
      work fine.

Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 170 insertions, 0 deletions

diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c
new file mode 100644
index 0000000000..939a38e6a8
--- /dev/null
+++ b/src/soc/intel/cannonlake/gpio_cnp_h.c
@@ -0,0 +1,170 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+#include <soc/pmc.h>
+
+static const struct reset_mapping rst_map[] = {
+	{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+};
+
+static const struct reset_mapping rst_map_com0[] = {
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
+};
+
+static const struct pad_group cnl_community0_groups[] = {
+	INTEL_GPP(GPP_A0, GPP_A0, GPP_A23),		/* GPP_A */
+	INTEL_GPP(GPP_A0, GPP_B0, GPP_B23),		/* GPP_B */
+};
+
+static const struct pad_group cnl_community1_groups[] = {
+	INTEL_GPP(GPP_C0, GPP_C0, GPP_C23),		/* GPP_C */
+	INTEL_GPP(GPP_C0, GPP_D0, GPP_D23),		/* GPP_D */
+	INTEL_GPP(GPP_C0, GPP_G0, GPP_G7),		/* GPP_G */
+};
+
+static const struct pad_group cnl_community2_groups[] = {
+	INTEL_GPP(GPD0, GPD0, GPD11),			/* GPD */
+};
+
+static const struct pad_group cnl_community3_groups[] = {
+	INTEL_GPP(GPP_K0, GPP_K0, GPP_K23),		/* GPP_K*/
+	INTEL_GPP(GPP_K0, GPP_H0, GPP_H23),		/* GPP_H */
+	INTEL_GPP(GPP_K0, GPP_E0, GPP_E12),		/* GPP_E */
+	INTEL_GPP(GPP_K0, GPP_F0, GPP_F23),		/* GPP_F */
+};
+
+static const struct pad_group cnl_community4_groups[] = {
+	INTEL_GPP(GPP_I0, GPP_I0, GPP_I14),		/* GPP_I */
+	INTEL_GPP(GPP_I0, GPP_J0, GPP_J11),		/* GPP_J */
+};
+
+static const struct pad_community cnl_communities[] = {
+	{ /* GPP A, B */
+		.port = PID_GPIOCOM0,
+		.first_pad = GPP_A0,
+		.last_pad = GPP_B23,
+		.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_AB",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map_com0,
+		.num_reset_vals = ARRAY_SIZE(rst_map_com0),
+		.groups = cnl_community0_groups,
+		.num_groups = ARRAY_SIZE(cnl_community0_groups),
+	}, { /* GPP C, D, G */
+		.port = PID_GPIOCOM1,
+		.first_pad = GPP_C0,
+		.last_pad = GPP_G7,
+		.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_CDG",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = cnl_community1_groups,
+		.num_groups = ARRAY_SIZE(cnl_community1_groups),
+	}, { /* GPD */
+		.port = PID_GPIOCOM2,
+		.first_pad = GPD0,
+		.last_pad = GPD11,
+		.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPD",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = cnl_community2_groups,
+		.num_groups = ARRAY_SIZE(cnl_community2_groups),
+	}, { /* GPP K, H, E, F */
+		.port = PID_GPIOCOM3,
+		.first_pad = GPP_K0,
+		.last_pad = GPP_F23,
+		.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_KHEF",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = cnl_community3_groups,
+		.num_groups = ARRAY_SIZE(cnl_community3_groups),
+	}, { /* GPP I, J */
+		.port = PID_GPIOCOM4,
+		.first_pad = GPP_I0,
+		.last_pad = GPP_J11,
+		.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_IJ",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = cnl_community4_groups,
+		.num_groups = ARRAY_SIZE(cnl_community4_groups),
+	}
+};
+
+const struct pad_community *soc_gpio_get_community(size_t *num_communities)
+{
+	*num_communities = ARRAY_SIZE(cnl_communities);
+	return cnl_communities;
+}
+
+const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
+{
+	static const struct pmc_to_gpio_route routes[] = {
+		{ PMC_GPP_A, GPP_A },
+		{ PMC_GPP_B, GPP_B },
+		{ PMC_GPP_C, GPP_C },
+		{ PMC_GPP_D, GPP_D },
+		{ PMC_GPP_E, GPP_E },
+		{ PMC_GPP_F, GPP_F },
+		{ PMC_GPP_G, GPP_G },
+		{ PMC_GPP_H, GPP_H },
+		{ PMC_GPP_I, GPP_I },
+		{ PMC_GPP_J, GPP_J },
+		{ PMC_GPP_K, GPP_K },
+		{ PMC_GPD, GPD },
+	};
+	*num = ARRAY_SIZE(routes);
+	return routes;
+}