diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-11-10 17:14:01 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-02-16 00:23:04 +0000 |
| commit | b716e550338e3da4dcbd9aedbd2c63695ffc8a99 (patch) | |
| tree | 8d991462f3822e6c27179e2c0101d9027f87c428 /src/soc/intel/cannonlake/gpio.c | |
| parent | 3faa2c802eaa1ab06c2817af1e234fd839a543c4 (diff) | |
soc/intel/cannonlake: Add missing GPIO pin definitions
Fill the missing GPIO pin definitions, includeing community 3.
Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22482
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/gpio.c')
| -rw-r--r-- | src/soc/intel/cannonlake/gpio.c | 30 |
1 files changed, 22 insertions, 8 deletions
diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 2ebe60b395..cf10e4940f 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -33,10 +33,10 @@ static const struct reset_mapping rst_map_com0[] = { }; static const struct pad_community cnl_communities[] = { - { /* GPP A, B, G */ + { /* GPP A, B, G, SPI */ .port = PID_GPIOCOM0, .first_pad = GPP_A0, - .last_pad = GPP_G7, + .last_pad = GPIO_RSVD_11, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -47,10 +47,10 @@ static const struct pad_community cnl_communities[] = { .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map_com0, .num_reset_vals = ARRAY_SIZE(rst_map_com0), - }, { /* GPP D, F, H */ + }, { /* GPP D, F, H, VGPIO */ .port = PID_GPIOCOM1, .first_pad = GPP_D0, - .last_pad = GPP_H23, + .last_pad = GPIO_RSVD_52, .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -75,17 +75,31 @@ static const struct pad_community cnl_communities[] = { .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), - }, { /* GPP C, E */ + }, { /* AZA, CPU */ + .port = PID_GPIOCOM3, + .first_pad = HDA_BCLK, + .last_pad = GPIO_RSVD_78, + .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GP_AC", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + }, { /* GPP C, E, JTAG, HVMOS */ .port = PID_GPIOCOM4, .first_pad = GPP_C0, - .last_pad = GPP_E23, - .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, + .last_pad = GPIO_RSVD_67, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_CE", + .name = "GPP_CEJ", .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), |