diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-09 21:34:05 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-17 21:13:29 +0000 |
| commit | 1c2b1b977ae4fb74435336b23ebb774f22563012 (patch) | |
| tree | d0a1bcab3f96489dcb21cc69160c942c4e0e962a /src/soc/intel/cannonlake/gpio.c | |
| parent | 748bfac734b0cabfa0e2684886e434ece4a077f1 (diff) | |
soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names
The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.
Also, see soc/intel/tigerlake for reference.
Change-Id: I59df09c8fd464e75f918455aa1972765abc51459
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/cannonlake/gpio.c')
| -rw-r--r-- | src/soc/intel/cannonlake/gpio.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 91ac47c0b5..8e08a4b80b 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -32,14 +32,14 @@ static const struct reset_mapping rst_map_com0[] = { * linux/drivers/pinctrl/intel/pinctrl-cannonlake.c */ static const struct pad_group cnl_community0_groups[] = { - INTEL_GPP_BASE(GPP_A0, GPP_A0, GPIO_RSVD_0, 0), /* GPP_A */ - INTEL_GPP_BASE(GPP_A0, GPP_B0, GPIO_RSVD_2, 32), /* GPP_B */ + INTEL_GPP_BASE(GPP_A0, GPP_A0, ESPI_CLK_LOOPBK, 0), /* GPP_A */ + INTEL_GPP_BASE(GPP_A0, GPP_B0, GSPI1_CLK_LOOPBK, 32), /* GPP_B */ INTEL_GPP_BASE(GPP_A0, GPP_G0, GPP_G7, 64), /* GPP_G */ - INTEL_GPP(GPP_A0, GPIO_RSVD_3, GPIO_RSVD_11), /* SPI */ + INTEL_GPP(GPP_A0, SPI0_IO_2, SPI0_CLK_LOOPBK), /* SPI */ }; static const struct pad_group cnl_community1_groups[] = { - INTEL_GPP_BASE(GPP_D0, GPP_D0, GPIO_RSVD_12, 96), /* GPP_D */ + INTEL_GPP_BASE(GPP_D0, GPP_D0, GSPI2_CLK_LOOPBK, 96), /* GPP_D */ INTEL_GPP_BASE(GPP_D0, GPP_F0, GPP_F23, 128), /* GPP_F */ INTEL_GPP_BASE(GPP_D0, GPP_H0, GPP_H23, 160), /* GPP_H */ INTEL_GPP_BASE(GPP_D0, CNV_BTEN, vSD3_CD_B, 192), /* VGPIO */ @@ -52,15 +52,15 @@ static const struct pad_group cnl_community2_groups[] = { /* This community is not visible to the OS */ static const struct pad_group cnl_community3_groups[] = { - INTEL_GPP(HDA_BCLK, HDA_BCLK, SSP1_TXD), /* AZA */ - INTEL_GPP(HDA_BCLK, GPIO_RSVD_28, GPIO_RSVD_38), /* CPU */ + INTEL_GPP(HDA_BCLK, HDA_BCLK, I2S1_TXD), /* AZA */ + INTEL_GPP(HDA_BCLK, HDACPU_SDI, TRIGGER_OUT), /* CPU */ }; static const struct pad_group cnl_community4_groups[] = { INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */ INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 288), /* GPP_E */ - INTEL_GPP(GPP_C0, GPIO_RSVD_13, GPIO_RSVD_21), /* JTAG */ - INTEL_GPP(GPP_C0, GPIO_RSVD_22, GPIO_RSVD_27), /* HVMOS */ + INTEL_GPP(GPP_C0, PCH_TDO, ITP_PMODE), /* JTAG */ + INTEL_GPP(GPP_C0, EDP_BKLTEN, CL_RST_B), /* HVMOS */ }; static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = { @@ -68,7 +68,7 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = { [COMM_0] = { .port = PID_GPIOCOM0, .first_pad = GPP_A0, - .last_pad = GPIO_RSVD_11, + .last_pad = SPI0_CLK_LOOPBK, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -128,7 +128,7 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = { [COMM_3] = { .port = PID_GPIOCOM3, .first_pad = HDA_BCLK, - .last_pad = GPIO_RSVD_38, + .last_pad = TRIGGER_OUT, .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -148,7 +148,7 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = { [COMM_4] = { .port = PID_GPIOCOM4, .first_pad = GPP_C0, - .last_pad = GPIO_RSVD_27, + .last_pad = CL_RST_B, .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, |