diff options
| author | Christian Walter <christian.walter@9elements.com> | 2020-05-06 09:18:37 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:01:29 +0000 |
| commit | e6e9fa6ef90bc62d645da942f3bdc7bdeb1c1930 (patch) | |
| tree | a490f437351fbd91424ec29224a646780bf5ffbd /src/soc/intel/cannonlake/fsp_params.c | |
| parent | 9ea70c02cd0e5e28f38136ebbb6dbad72ad177c7 (diff) | |
soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip options
Intel introduced the UPD VrPowerDeliveryDesign with Cannon Lake. The
BIOS needs to program VrPowerDeliverDesign configuration per platform
according to the platform capabilities to avoid incorrect
electrial/power parameters. This is only added for Cannon Lake.
Refer to document 599797 for more details.
Change-Id: I89b8dceb40fa6a9dc67b218e91bf728ff928b5a0
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41081
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index b432087a32..b7e9ad8d8b 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -459,6 +459,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) #endif } +#if !CONFIG(SOC_INTEL_COMETLAKE) + params->VrPowerDeliveryDesign = config->VrPowerDeliveryDesign; +#endif + dev = pcidev_path_on_root(SA_DEVFN_IGD); if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) params->PeiGraphicsPeimInit = 1; |