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| author | John Su <john_su@compal.corp-partner.google.com> | 2019-02-12 11:44:49 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-13 13:03:58 +0000 |
| commit | c8464748cdfc928568ae9b2541c0eae839967db0 (patch) | |
| tree | 6e96b0468016150582d40affad25ef669c818b03 /src/soc/intel/cannonlake/fsp_params.c | |
| parent | 025c575750f24b0815393f090ceb515e41cbba13 (diff) | |
mb/google/sarien/variants/sarien: Add GPIO H3 for DVT1
Follow Northbay and intermal project to add GPIO H3(CNVI_EN#) for DVT1.
BUG=b:123461432
TEST=Built and tested on sarien system
Change-Id: I580a6e094d84a7bada534b14c2b65ecf4b9942b0
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/fsp_params.c')
0 files changed, 0 insertions, 0 deletions