diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-03 07:25:59 +0300 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-07-04 09:48:22 +0000 |
| commit | 903b40a8a46b6e8d853f509480661c8174311f17 (patch) | |
| tree | fd07ccd13dd831f2a30fac410c89125ed9eae1ce /src/soc/intel/cannonlake/fsp_params.c | |
| parent | 9c0e14e7c43e85e99c0bbfdff72019d908de1711 (diff) | |
soc/intel: Replace uses of dev_find_slot()
To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.
Replace this with method that relies on bus topology
that walks the root bus only.
Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel/cannonlake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 783ebb7ab3..a58a97c060 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -51,7 +51,7 @@ static uint8_t get_param_value(const config_t *config, uint32_t dev_offset) { struct device *dev; - dev = dev_find_slot(0, serial_io_dev[dev_offset]); + dev = pcidev_path_on_root(serial_io_dev[dev_offset]); if (!dev || !dev->enabled) return PCH_SERIAL_IO_INDEX(PchSerialIoDisabled); @@ -178,7 +178,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchLockDownRtcMemoryLock = 0; /* SATA */ - dev = dev_find_slot(0, PCH_DEVFN_SATA); + dev = pcidev_path_on_root(PCH_DEVFN_SATA); if (!dev) params->SataEnable = 0; else { @@ -192,7 +192,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* Lan */ - dev = dev_find_slot(0, PCH_DEVFN_GBE); + dev = pcidev_path_on_root(PCH_DEVFN_GBE); if (!dev) params->PchLanEnable = 0; else { @@ -275,7 +275,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = dev_find_slot(0, PCH_DEVFN_USBOTG); + dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); if (dev) { if (!xdci_can_enable()) dev->enabled = 0; @@ -287,7 +287,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; /* Enable CNVi Wifi if enabled in device tree */ - dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI); + dev = pcidev_path_on_root(PCH_DEVFN_CNViWIFI); #if CONFIG(SOC_INTEL_COMETLAKE) if (dev) params->CnviMode = dev->enabled; @@ -314,7 +314,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(config->PcieRpHotPlug)); /* eMMC and SD */ - dev = dev_find_slot(0, PCH_DEVFN_EMMC); + dev = pcidev_path_on_root(PCH_DEVFN_EMMC); if (!dev) params->ScsEmmcEnabled = 0; else { @@ -329,7 +329,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } } - dev = dev_find_slot(0, PCH_DEVFN_SDCARD); + dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (!dev) { params->ScsSdCardEnabled = 0; } else { @@ -338,7 +338,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); } - dev = dev_find_slot(0, PCH_DEVFN_UFS); + dev = pcidev_path_on_root(PCH_DEVFN_UFS); if (!dev) params->ScsUfsEnabled = 0; else |