diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-02-20 11:49:45 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-02-22 09:56:37 +0000 |
| commit | e83d057c3ec3b9a34503008439275777849c0c6a (patch) | |
| tree | ab7e04792cf134c70382f1356b7486abfde10366 /src/soc/intel/cannonlake/finalize.c | |
| parent | f9eaede51848d28214b47ade110b20ceac8a53e2 (diff) | |
soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode
TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree.
Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/finalize.c')
| -rw-r--r-- | src/soc/intel/cannonlake/finalize.c | 54 |
1 files changed, 0 insertions, 54 deletions
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index df4def21e9..5216460e60 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -33,49 +33,12 @@ #include <soc/systemagent.h> #include <stdlib.h> -#define PSF_BASE_ADDRESS 0x300 -#define PCR_PSFX_T0_SHDW_PCIEN 0x1C -#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) - #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ #define CAM_CLK_EN (1 << 1) #define MIPI_CLK (1 << 0) #define HDPLL_CLK (0 << 0) -static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask) -{ - uint32_t reg32; - - reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id)); - pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask); -} - -static void disable_sideband_access(void) -{ - device_t dev; - u8 reg8; - uint32_t mask; - - dev = PCH_DEV_P2SB; - - /* Remove the host accessing right to PSF register range. */ - /* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to [1, 1, 1, 1] */ - mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); - pch_configure_endpoints(dev, 5, mask); - - /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ - reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2); - pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1)); -} - -static void pch_disable_heci(void) -{ - pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN, - PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); - disable_sideband_access(); -} - static void pch_enable_isclk(void) { pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); @@ -84,25 +47,8 @@ static void pch_enable_isclk(void) static void pch_handle_sideband(config_t *config) { - device_t dev = PCH_DEV_P2SB; - - if (!dev) - return; - - if (config->HeciEnabled && !config->pch_isclk) - return; - - /* unhide p2sb device */ - pci_write_config8(dev, PCH_P2SB_E0 + 1, 0); - - if (config->HeciEnabled == 0) - pch_disable_heci(); - if (config->pch_isclk) pch_enable_isclk(); - - /* hide p2sb device */ - pci_write_config8(dev, PCH_P2SB_E0 + 1, 1); } static void pch_finalize(void) |