diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2019-04-30 12:52:29 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-22 10:09:23 +0000 |
| commit | d93531bcc8a216d9bc82a7f13444833943a270d7 (patch) | |
| tree | f7ac9a2a3548dba92f526daa0f3da1f870264938 /src/soc/intel/cannonlake/finalize.c | |
| parent | fa6233daeb2bfb8b75bea9032c0839e2d5bcf60d (diff) | |
soc/intel/cannonlake: Dump ME f/w version and status information
At the end of device enable, print the ME f/w version number.
Before resume or loading payload, dump the ME's Host Firmware
Status registers.
BUG=b:131437724
BRANCH=none
TEST=Prints seemingly sane values on WHL and CML devices.
Change-Id: Ibeb3a2a85cd84c9baa45f90f20a3dcf69f7d5646
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32527
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/finalize.c')
| -rw-r--r-- | src/soc/intel/cannonlake/finalize.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 4dfd15bc4a..eb4c5c2c9d 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -26,6 +26,7 @@ #include <intelblocks/tco.h> #include <reg_script.h> #include <spi-generic.h> +#include <soc/me.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> @@ -94,6 +95,8 @@ static void soc_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); + dump_me_status(); + pch_finalize(); printk(BIOS_DEBUG, "Finalizing SMM.\n"); |