diff options
| author | Felix Singer <felixsinger@posteo.net> | 2020-12-20 19:44:18 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-11 17:23:53 +0000 |
| commit | d456f65056530faccca31b392ffaff7bcc0953b3 (patch) | |
| tree | 0528a0b95cd7ac09e28ea2ecd208f2f086255d3b /src/soc/intel/cannonlake/cpu.c | |
| parent | 5569bddf66b44caf88acb54ea4a5dc7c1286762a (diff) | |
{soc,vc,mb}/intel: Drop support for Cannon Lake SoC
Drop the support for the Intel Cannon Lake SoC for various reasons:
* Most people can't use coreboot on Cannon Lake, since the required FSP
binaries aren't publicly available. Given that FSP binaries for several
newer platforms have been released, it's very unlikely that Cannon Lake
FSP will ever be released.
* It seems there is no interest in this, since the reference mainboard
is the only available mainboard in tree.
Also, remove the related reference mainboard intel/cannonlake_rvp and
its FSP headers in intel/fsp2_0/cannonlake.
Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48775
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/cpu.c')
| -rw-r--r-- | src/soc/intel/cannonlake/cpu.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 61b19894eb..f4b72abe75 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -178,14 +178,6 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) msr_t msr2; /* - * CFL and WHL CPU die are based on KBL CPU so we need to - * have this check, where CNL CPU die is not based on KBL CPU - * so skip this check for CNL. - */ - if (!CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)) - return 0; - - /* * If PRMRR/SGX is supported the FIT microcode load will set the msr * 0x08b with the Patch revision id one less than the id in the * microcode binary. The PRMRR support is indicated in the MSR |