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authorSubrata Banik <subrata.banik@intel.com>2017-12-14 18:22:13 +0530
committerSubrata Banik <subrata.banik@intel.com>2017-12-22 01:41:30 +0000
commit47a655cde3bd667beede719e8f5163381810c1e8 (patch)
treea7c31e7b23fd86c5d826d1205d33f614684bb838 /src/soc/intel/cannonlake/cpu.c
parent9c3a7b6a17bfc00086a32691a486355093eed651 (diff)
soc/intel/common: Add missing SoC common function into SMM library
Modify SMM common code in order to accommodate SKL, CNL, APL, GLK SOC code. Change-Id: Ie9f90df3336c1278b73284815b5197400512c1d2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22869 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/cpu.c')
-rw-r--r--src/soc/intel/cannonlake/cpu.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index 2dffccb923..728ab9c379 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -26,6 +26,7 @@
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
+#include <soc/pm.h>
#include <soc/smm.h>
static void soc_fsp_load(void)
@@ -216,7 +217,7 @@ static void post_mp_init(void)
* Now that all APs have been relocated as well as the BSP let SMIs
* start flowing.
*/
- smm_southbridge_enable();
+ smm_southbridge_enable(PWRBTN_EN | GBL_EN);
/* Lock down the SMRAM space. */
smm_lock();