diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-28 01:10:40 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-12 20:59:17 +0000 |
| commit | bda02b0f2bd7deddff20b7b14418d508a6b24edb (patch) | |
| tree | 6696bb13fad8751eaf41f91082104c2cc82ab95b /src/soc/intel/cannonlake/cpu.c | |
| parent | 8c8b34996dbc1ec1be2b9d7f2ce9b4a1d532501c (diff) | |
soc/intel/cannonlake: Align cosmetics with Ice Lake
By ironing out cosmetic differences between Cannon Lake and Ice Lake,
comparing actual code differences using a diff tool becomes simpler.
Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.
Change-Id: I4d9f882f9f8af1245e937b0d47bc7e993547365f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src/soc/intel/cannonlake/cpu.c')
| -rw-r--r-- | src/soc/intel/cannonlake/cpu.c | 57 |
1 files changed, 29 insertions, 28 deletions
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 36d252e477..0c24535816 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -54,9 +54,10 @@ static void configure_isst(void) static void configure_misc(void) { - config_t *conf = config_of_soc(); msr_t msr; + config_t *conf = config_of_soc(); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ @@ -105,6 +106,33 @@ static void configure_dca_cap(void) } } +/* + * The emulated ACPI timer allows replacing of the ACPI timer + * (PM1_TMR) to have no impart on the system. + */ +static void enable_pm_timer_emulation(void) +{ + const struct soc_intel_cannonlake_config *config; + msr_t msr; + + config = config_of_soc(); + + /* Enable PM timer emulation only if ACPI PM timer is disabled */ + if (!config->PmTimerDisabled) + return; + /* + * The derived frequency is calculated as follows: + * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer + * frequency is used. + */ + msr.hi = (3579545ULL << 32) / CTC_FREQ; + /* Set PM1 timer IO port and enable */ + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TIMER, msr); +} + static void set_energy_perf_bias(u8 policy) { msr_t msr; @@ -155,33 +183,6 @@ static void configure_c_states(void) wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } -/* - * The emulated ACPI timer allows replacing of the ACPI timer - * (PM1_TMR) to have no impart on the system. - */ -static void enable_pm_timer_emulation(void) -{ - const struct soc_intel_cannonlake_config *config; - msr_t msr; - - config = config_of_soc(); - - /* Enable PM timer emulation only if ACPI PM timer is disabled */ - if (!config->PmTimerDisabled) - return; - /* - * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. - */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { |