diff options
| author | Jamie Chen <jamie.chen@intel.com> | 2019-12-20 17:28:38 +0800 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-01-08 05:46:16 +0000 |
| commit | 3ccae2b7cddde23056b3187f97ecf734473ba704 (patch) | |
| tree | 1a12c420e9beb895d946a0211755f2fd4da454ba /src/soc/intel/cannonlake/chip.h | |
| parent | 6bb9aaf93f40c8852bab933c968d5aef8bb68b32 (diff) | |
soc/intel/cannonlake: Add VR config for CML
Add VR config IccMax, DC and AC loadline defaults for CML.
Add cpu_pl2_4_cfg to switch two kinds of VR design.
BUG:b:145094963
BRANCH:none
TEST:build coreboot and fsp with enabled fw_debug.
Flashed to device and checked the log.
All VR configs were set correctly.
Change-Id: I3922bfad5c21dafc64fb05c7d9343b9835b58752
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 85c33db07b..07a67cd630 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -218,6 +218,15 @@ struct soc_intel_cannonlake_config { uint8_t TcoIrqSelect; uint8_t TcoIrqEnable; + /* CPU PL2/4 Config + * Performance: Maximum PLs for maximum performance. + * Baseline: Baseline PLs for balanced performance at lower power. + */ + enum { + baseline, + performance + } cpu_pl2_4_cfg; + /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ |