diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-09-05 18:16:21 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-13 22:56:09 +0000 |
| commit | 08231833232d9cf80072e77c3f039a303bd6ffbb (patch) | |
| tree | 9d46556c5b489ad8d5730b6a47356f51f25fa927 /src/soc/intel/cannonlake/chip.h | |
| parent | 1210026bda8ad1fa24d2f0a7625f5b2cd35662ed (diff) | |
soc/intel/cannonlake: Add serialio device config
Add SerialIO device mode configuration, device mode definition mirrored
from FSP.
Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21411
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 52a5fc13a3..6d16327f27 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -20,6 +20,7 @@ #include <intelblocks/gspi.h> #include <stdint.h> +#include <soc/serialio.h> #include <soc/usb.h> #include <soc/vr_config.h> @@ -200,6 +201,30 @@ struct soc_intel_cannonlake_config { */ uint32_t PrmrrSize; uint8_t PmTimerDisabled; + /* + * SerialIO device mode selection: + * + * Device index: + * PchSerialIoIndexI2C0 + * PchSerialIoIndexI2C1 + * PchSerialIoIndexI2C2 + * PchSerialIoIndexI2C3 + * PchSerialIoIndexI2C4 + * PchSerialIoIndexI2C5 + * PchSerialIoIndexSPI0 + * PchSerialIoIndexSPI1 + * PchSerialIoIndexSPI2 + * PchSerialIoIndexUART0 + * PchSerialIoIndexUART1 + * PchSerialIoIndexUART2 + * + * Mode select: + * PchSerialIoDisabled + * PchSerialIoPci + * PchSerialIoAcpi + * PchSerialIoHidden + */ + uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; }; typedef struct soc_intel_cannonlake_config config_t; |