diff options
| author | Gaggery Tsai <gaggery.tsai@intel.com> | 2019-02-18 20:32:11 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-21 11:29:46 +0000 |
| commit | d01a995cd3e1adfd5af28a980eedac1fee0dddc1 (patch) | |
| tree | 8efaba2a815f9ed2ffce8a2379fe59e68128187e /src/soc/intel/cannonlake/chip.h | |
| parent | 5620b105461cc18cf1439f02013153237f372b4b (diff) | |
src/soc/intel/cannonlake: Add PsysPmax setting
This patch feeds PsysPmax setting to FSP through UPD and adds a
psys_pmax member in chip information so that we can set PsysPmax
through DT. The PsysPmax needs to be set correctly mapping to maximum
system power. Otherwise, system performance would be limited due to
the default PsysPmax setting in FSP is only 21W.
BUG=None
BRANCH=None
TEST=Set psys_pmax to an example value eg 101 in DT && put debug code
in FSP to print the PsysPmax value before sending to Pcode, ensure
the setting is correctly programmed.
Change-Id: Ia88ea17bc661a388c5b9bc3e59abc27c9f262977
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/31505
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index cb9ad3827f..1f26f1e146 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -216,6 +216,8 @@ struct soc_intel_cannonlake_config { uint32_t tdp_psyspl3_dutycycle; /* PL4 Value in Watts */ uint32_t tdp_pl4; + /* Estimated maximum platform power in Watts */ + uint16_t psys_pmax; /* Intel Speed Shift Technology */ uint8_t speed_shift_enable; |