soc/intel/cannonlake: Add serialio device config

Add SerialIO device mode configuration, device mode definition mirrored
from FSP.

Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21411
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 25 insertions, 0 deletions

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 52a5fc13a3..6d16327f27 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -20,6 +20,7 @@
 
 #include <intelblocks/gspi.h>
 #include <stdint.h>
+#include <soc/serialio.h>
 #include <soc/usb.h>
 #include <soc/vr_config.h>
 
@@ -200,6 +201,30 @@ struct soc_intel_cannonlake_config {
 	 */
 	uint32_t PrmrrSize;
 	uint8_t PmTimerDisabled;
+	/*
+	 * SerialIO device mode selection:
+	 *
+	 * Device index:
+	 * PchSerialIoIndexI2C0
+	 * PchSerialIoIndexI2C1
+	 * PchSerialIoIndexI2C2
+	 * PchSerialIoIndexI2C3
+	 * PchSerialIoIndexI2C4
+	 * PchSerialIoIndexI2C5
+	 * PchSerialIoIndexSPI0
+	 * PchSerialIoIndexSPI1
+	 * PchSerialIoIndexSPI2
+	 * PchSerialIoIndexUART0
+	 * PchSerialIoIndexUART1
+	 * PchSerialIoIndexUART2
+	 *
+	 * Mode select:
+	 * PchSerialIoDisabled
+	 * PchSerialIoPci
+	 * PchSerialIoAcpi
+	 * PchSerialIoHidden
+	 */
+	uint8_t SerialIoDevMode[PchSerialIoIndexMAX];
 };
 
 typedef struct soc_intel_cannonlake_config config_t;